ADE7754ARRL datasheet(39/44 Pages) AD

39 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

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Gain Register (18h)

The Gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing

to the GAIN register. Table X below summarizes the functionality of each bit in the GAIN register .

Table X GAIN Register

Bit

Default

Location

Mnemonic

Value

Description

0-1

PGA1

These bits are used to select the Gain of the current channels inputs.

bit 1

bit 0

PGA1=1

PGA1=2

PGA1=4

Reserved

ABS

The sum of the absolute active energies is done in the ANERGY and LAENERGY

registers when this bit is set to logic one. The regular sum is done when this bit is set to

logic zero - default mode.

NOLOAD

The active energy of each phase is not accumulated in the total active energy registers if

the instantaneous active power is lower than the no-load threshold when this bit is set to

logic zero, this mode is selected by default.

RESERVED -

This is intended for factory testing only and should be left at zero.

5-6

PGA2

These bits are used to select the Gain of the voltage channels inputs.

bit 6

bit 5

PGA2=1

PGA2=2

PGA2=4

Reserved

RESERVED -

This is intended for factory testing only and should be left at zero.

CFNUM Register (25h)

The CF scaling numerator and the sign of the active energy per phase are defined by writing/reading to the CFNUM register.

Table XI below summarizes the functionality of each bit in the CFNUM register .

Table XI CFNUM Register

Bit

Default

Location

Mnemonic

Value

Description

0-Bh

C F N

CF Scaling Numerator register. The content of this register is used in the numerator of

CF output scaling.

NEGA

The sign of the phase A instantaneous active power is available in this bit. Logic zero and

Logic one correspond to Positive and negative active power respectively. The functionality

of this bit is enabled by setting bit 5 of the WATMode register to logic one. When disabled

NEGA is equal to its default value.

NEGB

The sign of the phase B instantaneous active power is available in this bit. Logic zero and

Logic one correspond to Positive and negative active power respectively. The functionality

of this bit is enabled by setting bit 4 of the WATMode register to logic one. When disabled

NEGB is equal to its default value.

NEGC

The sign of the phase C instantaneous active power is available in this bit. Logic zero and

Logic one correspond to Positive and negative active power respectively. The functionality

of this bit is enabled by setting bit 3 of the WATMode register to logic one. When disabled

NEGC is equal to its default value.

F h

RESERVED

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