Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

AD9821 Folha de dados(PDF) 4 Page - Analog Devices

Nome de Peças AD9821
Descrição Electrónicos  Complete 12-Bit 40 MSPS Imaging Signal Processor
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD9821 Folha de dados(HTML) 4 Page - Analog Devices

  AD9821 Datasheet HTML 1Page - Analog Devices AD9821 Datasheet HTML 2Page - Analog Devices AD9821 Datasheet HTML 3Page - Analog Devices AD9821 Datasheet HTML 4Page - Analog Devices AD9821 Datasheet HTML 5Page - Analog Devices AD9821 Datasheet HTML 6Page - Analog Devices AD9821 Datasheet HTML 7Page - Analog Devices AD9821 Datasheet HTML 8Page - Analog Devices AD9821 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 16 page
background image
REV. 0
–4–
AD9821
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter
To
Min
Max
Unit
AVDD1, AVDD2
AVSS
–0.3
+3.9
V
DVDD1, DVDD2
DVSS
–0.3
+3.9
V
DRVDD
DRVSS
–0.3
+3.9
V
Digital Outputs
DRVSS
–0.3
DRVDD + 0.3
V
DATACLK
DVSS
–0.3
DVDD + 0.3
V
CLPOB, PBLK
DVSS
–0.3
DVDD + 0.3
V
SCK, SL, SDATA
DVSS
–0.3
DVDD + 0.3
V
VRT, VRB
AVSS
–0.3
AVDD + 0.3
V
BYP1, VIN
AVSS
–0.3
AVDD + 0.3
V
Junction Temperature
150
°C
Lead Temperature
300
°C
(10 sec)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK Clock Period
tCONV
25
25
ns
DATACLK Hi/Low Pulsewidth
tADC
11
12.5
ns
CLPOB Pulsewidth
*
tCOB
220
Pixels
Internal Clock Delay
tID
3.0
ns
DATA OUTPUTS
Output Delay
tOD
13
16
ns
Output Hold Time
tH
7.0
7.6
ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
(CL = 20 pF, fSAMP = 40 MHz, Imager-Mode Timing in Figures 5 and 6, Serial Timing in Figures 7–9)
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD9821KST
–20
°C to +85°CThin Plastic
ST-48
Quad Flatpack
(LQFP)
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA = 56
°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9821 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Folha de dados Download

Go To PDF Page


Ligação URL



ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   Link para a ficha técnica    |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com