THC63LVDM83D_Rev.4.20_E

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THine Electronics, Inc.

Security E

CLK IN

90%

10%

90%

10%

t

TCIT

t

TCIT

LVCMOS & LVDS Transmitter AC Specifications

Over recommended operating supply and temperature range unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Unit

CLK IN Transition Time

-

-

5.0

ns

CLK IN Period

6.25

T

125

ns

CLK IN High Time

0.35T

0.5T

0.65T

ns

CLK IN Low Time

0.35T

0.5T

0.65T

ns

CLK IN to TCLK+/- Delay

-

3T

-

ns

LVCMOS Data SetuptoCLK IN

2.0

-

-

ns

LVCMOS Data Hold from CLK IN

0.0

-

-

ns

LVDS Transition Time

-

0.6

1.5

ns

Output Data Position0 (T=6.25ns ~ 20ns)

-0.15

0.0

+0.15

ns

Output Data Position1 (T=6.25ns ~ 20ns)

T/7-0.15

T/7

T/7+0.15

ns

Output Data Position2 (T=6.25ns ~ 20ns)

2T/7-0.15

2T/7

2T/7+0.15

ns

Output Data Position3 (T=6.25ns ~ 20ns)

3T/7-0.15

3T/7

3T/7+0.15

ns

Output Data Position4 (T=6.25ns ~ 20ns)

4T/7-0.15

4T/7

4T/7+0.15

ns

Output Data Position5 (T=6.25ns ~ 20ns)

5T/7-0.15

5T/7

5T/7+0.15

ns

Output Data Position6 (T=6.25ns ~ 20ns)

6T/7-0.15

6T/7

6T/7+0.15

ns

Phase Lock Loop Set

-

-

10.0

ms

*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

Table 7. LVCMOS & LVDS Transmitter AC Specifications

LVCMOS Input

Figure 5. CLKIN Transmission Time

LVDS Output

LVDS Output Load

Figure 6. LVDS Output Load and Transmission Time