ADC10D020 datasheet(9/32 Pages) NSC

9 / 32 page

Converter Electrical Characteristics (Continued)

The following specifications apply for V

A =VD =VDR = +3.0 VDC,VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (ac

coupled) = FSR = 1.0 V

P-P,CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS =50Ω,trc =tfc < 4 ns, NOT offset corrected.

Boldface limits apply for T

A =TMIN to TMAX: all other limits TA = 25˚C (Note 7).

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

Output Short Circuit Source

Current

OUT =0V

Parallel Mode

−7

Multiplexed Mode

−14

−I

Output Short Circuit Sink Current

OUT =VDR

Parallel Mode

Multiplexed Mode

POWER SUPPLY CHARACTERISTICS

A +ID

Core Supply Current

PD = LOW, STBY = LOW, dc input

47.6

mA(max)

PD = LOW, STBY = HIGH

8.8

PD = HIGH, STBY = LOW or HIGH

0.22

Digital Output Driver Supply

Current (Note 10)

PD = LOW, STBY = LOW, dc input

1.3

1.4

mA(max)

PD = LOW, STBY = HIGH

0.1

PD = HIGH, STBY = LOW or HIGH

0.1

PWR

Power Consumption

PD = LOW, STBY = LOW, dc input

150

169

mW(max)

PD = LOW, STBY = LOW, 1 MHz Input

178

PD = LOW, STBY = HIGH

PD = HIGH, STBY = LOW or HIGH

<1mW

PSRR1

Power Supply Rejection Ratio

Change in Full Scale with 2.7V to 3.6V Supply

Change

PSRR2

Power Supply Rejection Ratio

Rejection at output with 20 MHz, 250 mV

P-P

Riding on V

A and VD

AC Electrical Characteristics

OS = Low (Multiplexed Mode)

The following specifications apply for V

A =VD =VDR = +3.0VDC,VREF = 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN (ac

coupled) = FSR = 1.0 V

P-P,CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS =50Ω,trc =tfc < 4 ns, NOT offset corrected.

Boldface limits apply for T

A =TMIN to TMAX: all other limits TA = 25˚C (Note 7)

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

CLK1

Maximum Clock Frequency

MHz(min)

CLK2

Minimum Clock Frequency

MHz

Duty Cycle

%(min)

%(max)

Pipeline Delay (Latency)

I Data

2.5

Clock Cycles

Q Data

3.0

Clock Cycles

r,tf

Output Rise and Fall Times

Offset Correction Pulse Width

ns(min)

Output Delay from CLK Edge to

Data Valid

ns(max)

DIQ

I/Q Output Delay

SKEW

I/Q to Data Delay

±200

Sampling (Aperture) Delay

2.4

Aperture Jitter

<10

ps(rms)

VALID

Data Valid Time

Overrange Recovery Time

Differential V

IN step from 1.5V to

WUPD

PD Low to 1/2 LSB Accurate

Conversion (Wake-Up Time)

<1ms

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