X9521 datasheet(10/26 Pages) XICOR

10 / 26 page

REV 1.1.9 1/30/03

Characteristics subject to change without notice.

10 of 26

www.xicor.com

X9521

– Preliminary Information

The master terminates the Data Byte loading by issuing a

STOP condition, which causes the X9521 to begin the

nonvolatile write cycle. As with the byte write operation, all

inputs are disabled until completion of the internal write

cycle. See Figure 12 for the address, ACKNOWLEDGE,

and data transfer sequence.

Stops and EEPROM Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

and receiving the subsequent ACKNOWLEDGE signal. If

the master issues a STOP within a Data Byte, or before

the X9521 issues a corresponding ACKNOWLEDGE, the

X9521 cancels the write operation. Therefore, the con-

tents of the EEPROM array does not change.

EEPROM Array Read Operations

Read operations are initiated in the same manner as write

operations with the exception that the R/W bit of the Slave

Address Byte is set to one. There are three basic read

operations: Current EEPROM Address Read, Random

EEPROM Read, and Sequential EEPROM Read.

Current EEPROM Address Read

Internally the device contains an address counter that

maintains the address of the last word read incremented

by one. Therefore, if the last read was to address n, the

next read operation would access data from address n+1.

On power up, the address of the address counter is unde-

ﬁned, requiring a read or write operation for initialization.

Upon receipt of the Slave Address Byte with the R/W bit

set to one, the device issues an ACKNOWLEDGE and

then transmits the eight bits of the Data Byte. The master

terminates the read operation when it does not respond

with an ACKNOWLEDGE during the ninth clock and then

issues a STOP condition (See Figure 14 for the address,

ACKNOWLEDGE, and data transfer sequence).

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read opera-

tion, the master must either issue a STOP condition dur-

ing the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a STOP condition.

Another important point to note regarding the “Current

EEPROM Address Read” , is that this operation is not

available if the last executed operation was an access to a

DCP or the CONSTAT Register (i.e.: an operation using

address

5 bytes

7 bytes

address

= 6

address pointer

ends here

Addr = 7

Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.

5 bytes

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Figure 14. Current EEPROM Address Read Sequence

1 01 0 0 0 0

X9521 Folha de dados(PDF) 10 Page - Xicor Inc.

X9521 Folha de dados(HTML) 10 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Folha de dados Download

Ligação URL