8

 2002 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1544

PRELIMINARY

:

r

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b

m

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N

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G:

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P:

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T

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F

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D:

e

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F

1

8

1B

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5

d

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a

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D

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s

s

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2

9

1

)

1

(

V

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D

V

5e

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p

3

9

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1

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3

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3l

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3

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3e

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4

2

2B

S

V

5l

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D

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5

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.

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7

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3V

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This table shows which gate drive pin controls which MOS.ET:

Gates At A Glance

Notes:

(1) Note common pin for Gate 2 and Gate 3 - both .ETs are operating as pass devices only in S0.

(2) .ET is acting as a pass device for 3.3V Dual Memory and as a linear regulator for 2.5V Dual Memory.

m

e

t

s

y

S

e

t

a

t

S

B

S

UI

C

P3

S

/5

S

/K

O

_

R

W

Pl

a

u

D

V

5

.

2

/

V

3

.

3

y

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o

m

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M

V

3

.

3

l

a

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D

V

5

l

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5

.

1

/

V

3

.

3

P

G

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)

2

(

V

8

.

1

)

2

(

s

t

n

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m

m

o

C

0

1

(

1

(

11

1

V

3

.

3V

3

.

3V

5V

3

.

3V

3

.

3

3

1

(

1

(

01

0

B

S

V

5B

S

V

5B

S

V

5N

ON

O

5

S

0

000

0

F

F

OF

F

OF

F

ON

ON

Of

f

o

s

t

u

p

t

u

o

ll

A

01

0

0

0

F

F

OB

S

V

5F

F

ON

ON

Od

e

l

b

a

n

e

I

C

P

1

000

0

F

F

OF

F

OB

S

V

5N

ON

Od

e

l

b

a

n

e

B

S

U

11

0

0

0

F

F

OB

S

V

5B

S

V

5N

ON

OB

S

U

&

I

C

P

d

e

l

b

a

n

e

This table shows which output is powered from which supply under each system state.

Notes:

(1) X = “don’t care”. In S0 and S3, the 3.3V dual and 5V dual outputs are not affected by the state of the PCI and

USB pins. These outputs are only controlled by the sate of the PCI and USB pins in S5.

(2) Gate 7 and Gate 8 are high in all states with 5VSB > UVLO and OCP not tripped. If powered from 3.3V as shown

in the table, the AGP and 1.8V outputs are only present in S0, and will ramp with the 3.3V supply as it comes up.

This avoids dips in the 3.3V supply which would otherwise occur if Gate 7 and Gate 8 went high after the 3.3V

supply came up, demanding high currents to charge output capacitors. If powered from 5VSB they can be used to

create 1.5VSB, 1.8VSB or 3.3VSB as required.

Power Matrix