P9027LP-R Datasheet

© 2016 Integrated Device Technology, Inc

20

April 28, 2016

0xD5

FLT_RAW_2

2

R

0

“1” when End Of Charge (EOC) pin is set.

0xD5

FLT_RAW_1

1

R

0

Reserved

0xD5

FLT_RAW_0

0

R

0

“1” when enable (

EN

̅̅̅̅) pin is set high.

Enabled fault flag. If the fault condition exists and this fault is enabled in Masked Fault Enable Register, the bit for the fault in FLT_MSKD will

be set.

Table 14. Masked Fault Condition

Byte

Address

Byte Name

Bit

Field

Typical Default

Value

Description

0xD6

FLT_MSKD

7:5

R

0

Reserved.

0xD6

FLT_MSKD

4

R

0

Reserved.

0xD6

FLT_MSKD

3:0

R

0

Reserved

0xD7

FLT_MSKD

7

R

0

TS2 voltage is above programmed voltage. End of power transfer

packet sent (0x03) if triggered.

0xD7

FLT_MSKD

6

R

0

TS1 voltage is above programmed voltage. End of power transfer

packet sent (0x03) if triggered.

0xD7

FLT_MSKD

5

R

0

“1” when die temperature is greater than Tdie_shutdown. End of

power transfer packet sent (0x02) if triggered.

0xD7

FLT_MSKD

4

R

0

Reserved

0xD7

FLT_MSKD

3

R

0

Reserved

0xD7

FLT_MSKD

2

R

0

“1” when End of Charge (EOC) pin is set. End of power transfer

packet sent (0x01) if triggered.

0xD7

FLT_MSKD

1

R

0

Reserved

0xD7

FLT_MSKD

0

R

0

“1” when enable (

EN

̅̅̅̅) pin is set high. End of power transfer packet

sent (0x02) if triggered.

Enabled fault flag. If the fault condition exists and this fault is enabled in Masked Interrupt Enable Register, the bit for the fault in INTR_MSKD

will be set.

Table 15. Masked Interrupt Register

Byte

Address

Byte Name

Bit

Field Typical

Default

Value

Description

0xD8

INTR_MSKD

7:5

R

0

Reserved.

0xD8

INTR_MSKD

4

R

0

Reserved.

0xD8

INTR_MSKD

3:0

R

0

Reserved

0xD9

INTR_MSKD

7

R

0

TS2 voltage is above programmed voltage, INT pin

will be toggled.