ADSP-BF705BBCZ-4 datasheet(72/116 Pages) AD

72 / 116 page

Rev. A

Page 72 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

DDR2 SDRAM Write Cycle Timing

Table 41 and Figure 19 show DDR2 SDRAM write cycle timing, related to the dynamic memory controller (DMC).

Table 41. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V

200 MHz1

1 To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.

Parameter

Min

Max

Unit

Switching Characteristics

tDQSS

2 Write command to first DMC0_DQS delay = WL × tCK + tDQSS.

DMC0_DQS Latching Rising Transitions to Associated Clock Edges

–0.25

+0.25

tCK

tDS

Last Data Valid to DMC0_DQS Delay

0.15

tDH

DMC0_DQS to First Data Invalid Delay

0.275

tDSS

DMC0_DQS Falling Edge to Clock Setup Time

0.2

tCK

tDSH

DMC0_DQS Falling Edge Hold Time From DMC0_CK

0.2

tCK

tDQSH

DMC0_DQS Output High Pulse Width

0.35

tCK

tDQSL

DMC0_DQS Output Low Pulse Width

0.35

tCK

tWPRE

Write Preamble

0.35

tCK

tWPST

Write Postamble

0.4

tCK

tIPW

Address and Control Output Pulse Width

0.6

tCK

tDIPW

DMC0_DQ and DMC0_DM Output Pulse Width

0.35

tCK

Figure 19. DDR2 SDRAM Controller Output AC Timing

tDS

tDH

tDQSS

tDSH

tDSS

tWPRE

tDQSL

tDQSH

tWPST

DMC0_LDM

DMC0_CK

tIPW

tDIPW

DMC0_UDM

DMC0_LDQS

DMC0_UDQS

DMC0_CK

DMC0_Ax

DMC0 CONTROL

DMC0_DQx

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