IRLIB9343 datasheet(6/7 Pages) IRF

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IRLIB9343

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Fig 19a. Gate Charge Test Circuit

Fig 19b Gate Charge Waveform

Vds

Vgs

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 16.

Peak Diode Recovery dv/dt Test Circuit for P-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple

≤ 5%

Body Diode

Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D =

P.W.

Period

* VGS = 5V for Logic Level Devices

VDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T

Inductor

Current

VCC

DUT

Fig 17b. Unclamped Inductive Waveforms

Fig 17a. Unclamped Inductive Test Circuit

V(BR)DSS

IAS

0.01

Ω

D.U.T

VDS

VDD

DRIVER

15V

-20V

-VGS

Fig 18b. Switching Time Waveforms

Fig 18a. Switching Time Test Circuit

VDS

90%

10%

VGS

td(on)

td(off)

* Reverse Polarity of D.U.T for P-Channel

VDS

-10V

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

VDD

D.U.T.

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