10

PCM_ALWAYS_ON

This bit should be set if another codec is using the PCM bus. When set, the LM4930 will

drive the clock and sync signals in all modes except Powerdown (Note 12)

11

I2S_M/S

I2S master or slave select. If set then I2S = master. Cleared = slave

12

I2S_RES

I2S resolution select. If set then 32 bits per frame. If cleared then 16 bits per frame

13

RSVD

RESERVED (Note 13)

14

RSVD

RESERVED (Note 13)

15

RSVD

RESERVED (Note 13)

Voice/Test Config Registers

This register configures the voiceband codec, sidetone attenuation, and selected control functions. The 7 bit address for the

VOICE TESTCONFIG register is XX10001.

(X=0if ADDR is set to logic 0)

(X=1if ADDR is set to logic 1)

VOICETESTCONFIG (XX10001).

(Set = logic 1, Clear = logic 0)

BIT

15

14

13

12

11

10

987654321

0

RESET

0

0

0000000000000

0

Address

Register

Description

0

CLASS

If set, configures the chip for use with an external class D or linear amplifier and turns the

BTL speaker output into a buffer. (Note 12)

4:1

SIDESTONE_ATTEN Programs the attenuation of the digital sidetone. Attenuation is set as follows:

4:1

Sidetone

Attenuation

4:1

Sidetone Attenuation

0000

Mute

1000

-9dB

0001

-30dB

1001

-6dB

0010

-27dB

1010

-3dB

0011

-24dB

1011

0dB

0100

-21dB

1100

Mute

0101

-18dB

1101

Mute

0110

-15dB

1110

Mute

0111

-12dB

1111

Mute

5

AUTOSIDE

This feature is included for use with the mono speaker in hands-free applications where

sidetones may not be desirable. If set, the sidetone is always muted in voice over mono

speaker modes (0010, 0100, 1001, and 1010), otherwise the sidetone is present at whatever

level is set in the gain control register

6

CLOCK_DIV

If set, allows for the use of a 24.576MHz crystal. Default setting is for 12.288MHz crystal.

(Note 12)

7

ZXD_DISABLE

Disables the zero crossing detect in the stereo DAC to guarantee immediate mode changes

rather than waiting for a zero cross. (Note 11)

8:9

RSVD

RESERVED (Note 13)

10:11

CAP_SIZE

Set to accomodate different bypass capacitor values to give correct turn-off delay and

click/pop performance. Value is set as follows: (Note 12)

10:11

Delay

Bypass Capacitor Size

00

25ms

0.1µF

01

50ms

0.39µF

10

85ms

1µF

11

RESERVED

RESERVED

12

ZXDS_SLOW

If set, this forces the stereo DAC outputs to wait for a zero crossing before powering down

13

MUTE_LS

If set, mutes the loudspeaker amplifier in any mode where it is not already muted

14

MUTE_HP

If set, mutes the headphone amplifier in any mode where it is not already muted

15

MUTE_MIC

If set, mutes the microphone preamp

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