DLPR910

GND

OE/RESET

VCCINT

VCCO

CLK

CE

CF

CEO

DO

EN_EXT_SEL

REV_SEL0

REV_SEL1

TCK

TDI

TDO

TMS

VCCJ

7

DLPR910

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DLPS065B – SEPTEMBER 2015 – REVISED NOVEMBER 2016

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7 Detailed Description

7.1 Overview

The configuration bit stream stored in the DLPR910 supports reliable operation of the DLPC910 with the

DLP9000X DMD or the DLP6500 family of DMDs. The DLPC910 digital controller loads this configuration bit

stream from the DLPR910.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Data Interface

7.3.1.1 Data Outputs

The DLPR910 is configured for serial mode operation, where D0 is the data output pin. D0 output pin provides a

serial connection to the DLPC910, where the configuration is read out by the DLPC910.

7.3.1.2 Configuration Clock Input

The configuration CLK is connected to the DLPC910 in master mode, where the DLPC910 provides the clock

pulses to read the configuration from the DLPR910.