LM4550 datasheet(21/25 Pages) NSC

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Application Information (Continued)

Extended Audio ID Register (28h)

This read only register identifies which AC97 Extended Au-

dio features are supported. The LM4550 features AMAP

(Slot/DAC mappings based on codec ID), VRA (Variable

Rate Audio), and Multiple Codec support. AMAP is indicated

by a "1" in bit 9, VRA is indicated by a "1" in the LSB of

codec configuration as connected via external pins 45 and

46. Note that the external logic connection to pins 45 and 46

are inverse in polarity to the internal register setting.

Pin46 (ID1)

Pin45 (ID0)

Reg 28h ID1

Reg 28h ID0

Codec Mode

NC (not connected)

Primary

NC/DV

Primary

NC/DV

GND

Secondary 1

GND

NC/DV

Secondary 2

GND

Secondary 3

Extended Audio Status/Control Register (2Ah)

This read/write register provides status and control of the

Variable Sample Rate function. Setting the LSB of this reg-

ister to "1" enables Variable Rate Audio (VRA) mode and

allows DAC and ADC sample rates to be programmed via

registers 2Ch and 32h.

BIT

Function

VRA

0 = VRA off (48kHz fixed), 1 = VRA on

Sample Rate Control Registers (2Ch, 32h)

These read/write registers are used to set the sample rate

for the left and right channels of the DAC (2Ch) and the ADC

(32h). When Variable Rate Audio is enabled via bit-0 of

increments, to be any value from 4kHz to 48kHz. Below is a

list of the most common sample rates and their correspond-

ing register values.

SR15:SR0

Sample Rate (Hz)

1F40h

8000

2B11h

11025

3E80h

16000

5622h

22050

AC44h

44100

BB80h

48000

Chain-in Control Register (74h)

This register is only needed when using the Chain-in feature.

This feature goes beyond the AC ’97 specification and is not

required for standard AC-Link operation. The two LSBs of

this register default to the codec ID at codec reset. This

default state corresponds to standard AC-Link operation: the

output of codec pin 8 SDATA_IN is the output AC-Link frame

corresponding to the codec.

If the two LSBs are made not equal to the codec’s ID

(register 28h describes codec ID), then the signal present at

pin 48 CHAIN_IN is switched through and output at pin 8

SDATA_IN. In this fashion, secondary codecs can be

chained together by connecting one codec’s SDATA_IN pin

to the next codec’s CHAIN_IN pin. This has the end result of

only requiring a single SDATA_IN pin on the controller chip

instead of the standard one SDATA_IN pin per codec.

The last codec in the serial chain should have its CHAIN_IN

pin connected to digital ground. When writing the software,

care should be taken to avoid any problems that could occur

when the last codec in the chain is set to pass a chain-in

signal when there is none to pass. Different controllers may

handle a stream of all 0s differently and leaving the CHAI-

N_IN pin floating is definitely to be avoided.

Reserved Registers

Do not write to these registers as they are reserved.

AC’97 2.1 Multiple Codec

There can be up to four Codecs on the extended AC-link.

Multiple Codec AC-link implementations must run off a com-

mon BIT_CLK generated by the primary Codec. All four

codecs

will

controller

pins

such

as,

SYNC,

SDATA_OUT, and RESET# from the AC’97 Digital Control-

ler. Each device however, requires its own SDATA_IN pin

back to the controller.

ID pins 45 and 46 are internally pulled up to V

DD. For

example to configure the Codec as a primary the ID pins

could be either left floating or pulled up.

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