Package Outline and Connection Diagrams

20039103

Bottom View

16 Bump micro SMD Package

See NSC Package Number TLA16AAA

20039104

Note: The actual physical placement of the package marking will vary from

part to part. The package marking “XY” will designate the date code, “TT” is

a NSC internal code for die traceability. Both will vary considerably. L8B

identifies the device.

Top View

Pin Description

Pin Name

micro SMD

Bump Identifier

Logic Level

Function

A1

C4

1.8V

1.8V I/O Channel, (Note 1)

A2

D4

1.8V

1.8V I/O Channel, (Note 1)

A3

D3

1.8V

1.8V I/O Channel, (Note 1)

B1

C1

2.85V

2.85V I/O Channel, (Note 1)

B2

D1

2.85V

2.85V I/O Channel, (Note 1)

B3

D2

2.85V

2.85V I/O Channel, (Note 1)

DIR1

B3

1.8V

Direction control input Channel 1: ‘1’: A

→B; 0; B→A

DIR2

B2

1.8V

Direction control input Channel 2: ‘1’: A

→B; 0; B→A

DIR3

C3

1.8V

Direction control input Channel 3: ‘1’: A

→B; 0; B→A

V

CCA

B4

IC supply to the 1.8V side

V

CCB

B1

IC supply, 2.85V output from LDO

V

BAT

A1

LDO supply, Battery voltage

GND

A3

Power ground connection

EN1

A4

1.8V

Mode pin 1, see Table 1 for modes and settings

EN2

A2

1.8V

Mode pin 2, see Table 1 for modes and settings

LatchClk

C2

2.85V

Clock input: rising edge latches B inputs (DIR=0, normal mode)

Note 1: Pin pairs A1–B1, A2–B2 and A3–B3 form 3 independent bi-directional level-shifting channels.

TABLE 1. Operation Modes

Inputs

State

EN1

EN2

0

0

Level shifter off: High Z state on A

0

1

Level shifter off: High Z state on A

1

0

Latch bypassed in B to A direction, LDO=on (Note 2)

1

1

ON, normal mode (latch active)

Note 2: LatchClk is not used here. It should not be left floating.

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