SST25PF080B datasheet(13/32 Pages) MICROCHIP

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DS20005137B-page 13

SST25PF080B

FIGURE 4-12:

64-KBYTE BLOCK-ERASE SEQUENCE

4.5.9

CHIP-ERASE

The Chip-Erase instruction clears all bits in the device

to FFH. A Chip-Erase instruction will be ignored if any

of the memory area is protected. Prior to any Write oper-

ation, the Write-Enable (WREN) instruction must be exe-

cuted. CE# must remain active low for the duration of

the Chip-Erase instruction sequence. The Chip-Erase

instruction is initiated by executing an 8-bit command,

60H or C7H. CE# must be driven high before the instruction

is executed. The user may poll the Busy bit in the software

status register or wait TCE for the completion of the

internal self-timed Chip-Erase cycle. See Figure 4-13

for the Chip-Erase sequence.

FIGURE 4-13:

CHIP-ERASE SEQUENCE

4.6

Read Security ID

To execute a Read SID operation, the host drives CE#

low, sends the Read Security ID command cycle (88H),

one address cycle, and then one dummy cycle. Each

cycle is eight clock periods long, most significant bit

first.

After the dummy cycle, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The data output stream is contin-

uous through all SID addresses until terminated by a

low-to-high transition on CE#. The internal address

pointer automatically increments until the last SID

address is reached, then outputs 00H until CE# goes

high.

4.7

Lockout Security ID

The Lockout SID instruction prevents any future

changes to the Security ID. To execute a Lockout SID,

the host drives CE# low, sends the Lockout SID com-

mand cycle (85H), then drives CE# high. Each cycle is

eight clocks long, most significant bit first. Poll the

BUSY bit in the software status register, or wait TPSID,

for the completion of the Lockout SID operation.

CE#

SCK

ADDR

01 2 3 4 5 6 7 8

ADDR

HIGH IMPEDANCE

15 16

23 24

MODE 0

MODE 3

25137 63KBlkEr.0

MSB

CE#

SCK

01 2 3 4 5 6 7

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

25137 ChEr.0

MSB

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