SSRAM

AS5SS256K36

AS5SS256K36

Rev. 4.4 10/13

Micross Components reserves the right to change products or specifications without notice.

13

NOTE:

1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.

3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable

inputs being sampled.

4. ADV\ must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW.

WRITE TIMING

CLK

ADSP\

ADSS

ADSC\

ADDRESS

BWE\

BWa\ - BWd\

CE\

(See Note)

ADV\

OE\

t

ADSH

tAS

tAH

tDS

Single WRITE

BURST WRITE

GW\

D

Extended BURST WRITE

t

A3

D(A2)

D(A2+1)

D(A2+2)

D(A2+3)

D(A3)

D(A3+1)

D(A3+2)

D(A1)

D(A2+1)

t

KC

t

KL

t

KH

Q

High-Z

ADSS

t

ADSH

t

A1

A2

BYTE WRITE signals are

ignored when ADSP\ is LOW.

ADSS

t

ADSH

t

BURST READ

ADSC\ extends burst.

WS

t WH

t

WS

t WH

t

(Note 5)

CES

tCEH

t

(Note 4)

AAS

tAAH

t

ADV\ suspends burst.

(Note 3)

tDH

tOEHZ

(Note 1)

Don’t Care

Undefined