STM32L475VC datasheet(51/193 Pages) STMICROELECTRONICS

51 / 193 page

DocID027692 Rev 2

51/193

STM32L475xx

Functional overview

The major features are:

•

Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

•

8 host channels with periodic OUT support

•

HNP/SNP/IP inside (no need for any external resistor)

•

Software configurable to OTG 1.3 and OTG 2.0 modes of operation

•

OTG 2.0 Supports ADP (Attach detection Protocol)

•

USB 2.0 LPM (Link Power Management) support

•

Battery Charging Specification Revision 1.2 support

•

Internal FS OTG PHY support

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected.

3.34

Flexible static memory controller (FSMC)

Flexible static memory controller (FSMC) is also named Flexible memory controller (FMC).

The main features of the FMC controller are the following:

•

Interface with static-memory mapped devices in multiplexed mode including:

–

Static random access memory (SRAM)

–

NOR Flash memory

–

PSRAM

•

8-,16- bit data bus width

•

Write FIFO

•

The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

3.35

Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external flash is memory mapped and is seen by the

system as if it were an internal memory

STM32L475VC Folha de dados(PDF) 51 Page - STMicroelectronics

STM32L475VC Folha de dados(HTML) 51 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL