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STM32L072CZ Folha de dados(PDF) 96 Page - STMicroelectronics

Nome de Peças STM32L072CZ
Descrição Electrónicos  Ultra-low-power 32-bit MCU ARM-based Cortex-M0, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, USB, ADC, DACs
PDF  147 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
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STM32L072CZ Folha de dados(HTML) 96 Page - STMicroelectronics

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Electrical characteristics
STM32L072xx
96/147
DocID027100 Rev 3
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 28 and
Table 62, respectively.
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 26.
Table 62. I/O AC characteristics(1)
OSPEEDRx[1:0]
bit value(1)
Symbol
Parameter
Conditions
Min
Max(2) Unit
00
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
100
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
320
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
0.6
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
65
10
Fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
13
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
28
11
Fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
35
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
10
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
6
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
17
Fm+
configuration(4)
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 2.5 V to 3.6 V
-1
MHz
tf(IO)out
Output fall time
-
10
ns
tr(IO)out
Output rise time
-
30
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD = 1.65 V to 3.6 V
-350
KHz
tf(IO)out
Output fall time
-
15
ns
tr(IO)out
Output rise time
-
60
-tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-8
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 28.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed
description of Fm+ I/O configuration.



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