ADCMP380

Data Sheet

THEORY OF OPERATION

The ADCMP380 ultralow power voltage comparator is especially

suited for battery-powered applications due to its maximum

190 nA quiescent current. The internal precision reference

and the low input leakage current allow the user to monitor the

voltage of interest accurately through external resistor dividers.

The device features internal input hysteresis and an open-drain

output. The output remains logic high after the voltage on the

IN pin is above the internal reference voltage. The device keeps

the output in a logic low state whenever the supply voltage on

the VCC pin is below the UVLO threshold. The output can be

disabled, and it remains low if the EN pin is pulled low, regardless

of the status of the IN pin.

TRANSIENT IMMUNITY

To avoid unnecessary output state change caused by fast power

supply transients, an input glitch filter is added to the IN pin of

the ADCMP380 to filter out the transient glitches on the pin.

Figure 8 shows the comparator overdrive (that is, the maximum

magnitude of positive and negative going pulses with respect to

the reference voltage) vs. the pulse duration without changing

the state of the output.

OUTPUT

The output of ADCMP380 comparator is open-drain. The

when the device exits ULVO.

When the IN voltage falls below the internal reference voltage,

the OUT pin asserts low within 23 μs (typical). When the

monitored voltage rises above the reference voltage plus

hysteresis, the OUT pin asserts high within 39.5.

EN INPUT

Driving EN low asserts the output low. The EN input has a

0.6 MΩ internal pull-up resistor so that the input is always high

when unconnected. To drive the EN input, use an external signal

or a push-button switch to ground; debounce circuitry is integrated

on-chip for this purpose. Noise immunity is provided on the EN

input, and fast, negative going transients of up to 0.4 μs (typical) are

ignored. If required, a 0.1 μF capacitor between the EN pin and

ground provides additional noise immunity.

Figure 14. Timing Diagram

ADDING HYSTERESIS

To prevent oscillations at the output caused by noise or slowly

moving signals passing the switching threshold, positive feedback

can be used to add hysteresis to the input.

For the configuration shown in Figure 15, connect the bottom

end of the input resistor divider to the output; the effective

threshold is altered based on the output state.

The input falling threshold level is given by

(

)

PULLUP

SUPPLY

PULLUP

REF

FALL

IN

R

R2

R1

V

R

R2

R1

V

V

+

+

+

=

–

_

The input rising threshold level is given by

(

)

R2

R2

R1

V

V

REF

RISE

IN

+

=

_

The additional hysteresis is the difference between these voltage

levels and is given by

PULLUP

SUPPLY

PULLUP

REF

IN

R

R2

R2

R2

R1R2

V

R1R

V

V

×

+

×

+

=

∆

Note that the built-in hysteresis of the device is neglected in this

calculation.

Figure 15. Configuration with Added Hysteresis

VCC

OUT

EN

EN EXTERNALLY

DRIVEN LOW

IN

IN

R1

R2

VCC

EN

GND

OUT

REF

ADCMP380

Rev. 0 | Page 8 of 10