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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ST72754 Folha de dados(PDF) 59 Page - STMicroelectronics |
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ST72754 Folha de dados(HTML) 59 Page - STMicroelectronics |
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59 / 144 page  ST72774/ST727754/ST72734 59/144 SYNC PROCESSOR (SYNC) (Cont’d) ClampOut and Moire Signal Clamp Output signal The clamping pulse generator can control the pulse width and polarity signal and can be configured as pseudo-front porch or back porch. To use the ClampOut signal: – Select the Clamping Pulse width: BP0/BP1 bits in MCR register – Program the Clamp polarity: CLPINV bit in POLR register – Select the ClampOut signal as back-porch (after falling edge of HSYNCO) or pseudo-front porch (after the rising edge of HSYNCO): HS0/HS1 bits in MCR register. – Enable the CLAMPOUT signal: CLMPEN bit in ENR register Moire Signal The Moire output signal is available (instead of the clamping signal) to reduce the screen Moire effect and improve color transitions. The CLAMPOUT pin is alternatively used to output a Moire signal. The output signal toggles at each HFBACK rising edge. After each VFBACK falling edge, the value of the Moire output is the opposite of the previous one, independent of the number of HFBACK pulses during the VFBACK low level. To use the Moire signal: – Select the Moire signal: Reset the BP0/BP1 bits in MCR register – Enable the output signal: CLMPEN bit in ENR register Figure 40. Clamping Pulse (CLAMPOUT) Delay HSYNCO CLAMPOUT Maximum delay: Programmable clamping width: 0, 167ns, 333ns, 666ns - (Fixed delay of 10 to 30ns) + (fOSC/2) = approx. 110ns. |
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