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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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PSOC4100M Folha de dados(PDF) 1 Page - Cypress Semiconductor |
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PSOC4100M Folha de dados(HTML) 1 Page - Cypress Semiconductor |
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1 / 41 page  PSoC® 4: PSoC 4100M Family Datasheet Programmable System-on-Chip (PSoC®) Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-96519 Rev. *E Revised August 19, 2016 General Description PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4100M product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic, programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode, and standard communication and timing peripherals. The PSoC 4100M products will be fully compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem ■ 24-MHz ARM Cortex-M0 CPU with single-cycle multiply ■ Up to 128 kB of flash with Read Accelerator ■ Up to 16 kB of SRAM ■ DMA engine Programmable Analog ■ Four opamps that operate in Deep Sleep mode at very low current levels ■ All opamps have reconfigurable high current pin-drive, high-bandwidth internal drive, ADC input buffering, and Comparator modes with flexible connectivity allowing input connections to any pin ■ Four current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ Two low-power comparators that operate in Deep Sleep mode ■ 12-bit SAR ADC with 806-Ksps conversion rate Low Power 1.71 to 5.5 V Operation ■ 20-nA Stop Mode with GPIO pin wakeup ■ Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs Capacitive Sensing ■ Cypress Capacitive Sigma-Delta (CSD) technique provides best-in-class SNR (>5:1) and water tolerance ■ Cypress-supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning (SmartSense™) Segment LCD Drive ■ LCD drive supported on all pins (common or segment) ■ Operates in Deep Sleep mode with 4 bits per pin memory Serial Communication ■ Four independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Timing and Pulse-Width Modulation ■ Eight 16-bit timer/counter pulse-width modulator (TCPWM) blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Package Options ■ 68-pin QFN, 64-pin TQFP wide and narrow pitch, and 48-pin and 44-pin TQFP packages ■ Up to 55 programmable GPIOs ■ GPIO pins can be CapSense, LCD, analog, or digital ■ Drive modes, strengths, and slew rates are programmable Extended Industrial Temperature Operation ■ –40 °C to +105 °C operation PSoC Creator Design Environment ■ Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) ■ Applications Programming Interface (API component) for all fixed-function and programmable peripherals Industry-Standard Tool Compatibility ■ After schematic entry, development can be done with ARM-based industry-standard development tools |
Nº de peça semelhante - PSOC4100M |
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Descrição semelhante - PSOC4100M |
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