FEDL610Q461-03

ML610Q461/ML610Q462/ML610Q463

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• Timers

− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)

− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)

• Capture

− Time base capture × 2 channels (4096 Hz to 32 Hz)

• PWM

− Resolution 16 bits × 1 channel

• Synchronous serial port

− Master/slave selectable × 1 channel

− LSB first/MSB first selectable

− 8-bit length/16-bit length selectable

• UART

− Half-Duplex Communication

− TXD/RXD × 1 channel

− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits

− Positive logic/negative logic selectable

− Built-in baud rate generator

• RC oscillation type A/D converter

− 16-bit counter

− Time division × 2 channels

• General-purpose ports

− Input-only port × 5 channels (including secondary functions)

− Output-only port

ML610Q461 : 10 channels (including secondary functions)

ML610Q462 : 6 channels (including secondary functions)

ML610Q463 : 2 channels (including secondary functions)

− Input/output port × 14 channels (including secondary functions)

• LCD driver

− The number of segments

ML610Q461 : 64 dots max. (16seg

×4com)

ML610Q462 : 80 dots max. (20seg

×4com)

ML610Q463 : 96 dots max. (24seg

×4com)

− 1/1 to 1/4 duty

− 1/2, 1/3 bias (built-in bias generation circuit)

− Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz

− Bias voltage multiplying clock selectable (8 types)

− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable

• Reset

− Reset through the RESET_N pin

− Power-on reset generation when powered on

− Reset when oscillation stop of the low-speed clock is detected

− Reset by the watchdog timer (WDT) overflow

• Clock

− Low-speed clock: Crystal oscillation (32.768 kHz)

(This LSI can not guarantee the operation withoug low-speed crystal oscillation clock)

− High-speed clock: Built-in RC oscillation (500 kHz, 2MHz)