LP3936SL datasheet(7/20 Pages) NSC

7 / 20 page

Logic Interface Characteristics

(1.8V

≤ V

DD_IO

≤ V

DD1,2) (Note 11)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL

Input Low Level

0.5

Input High Level

DD_IO − 0.5

Logic Input Current

−1.0

1.0

µA

SCL

Clock Frequency

2C Mode

400

kHz

MicroWire Mode

MHz

LOGIC OUTPUTS DO, CS

Output Low Level

DO, CS =3mA

0.3

0.6

Output High Level

DO =−3mA

DD_IO − 0.6

DD_IO − 0.3

Output Leakage Current

DO = 2.8V

1.0

µA

Note 11: In I2C mode operating ratings are limited to 3.0V

≤ VDD1,2 ≤ 4.5V and –20˚C ≤ TA ≤ +85˚C.

Control Interface

The LP3936 supports two different interfaces modes:

1) MicroWire/SPI interface

2) I

2C compatible interface

User can define the interface by MW_SEL pin. The pin

configuration will also change depending on which interface

is selected. The following table shows the selections for both

interface modes.

MW_SEL

Interface

Pin Configuration

Comment

MicroWire/SPI

SCL

(clock)

(data in)

(data out)

(chip select)

2C Compatible

SCL

CS = SDA

(clock)

(data in/out)

Use pull up resistor for SCL

Use pull up resistor for SDA

MicroWire/SPI Interface

The Microwire transmission consists of 16-bit Write and

Read Cycles. One cycle consists of 7 Address bits, 1 Read/

Write (R/W) bit and 8 Data bits. Read is done in two cycles:

address is provided in the first cycle and the data is sent out

on the next cycle. R/W bit high state defines a Write Cycle

and low defines a Read Cycle. DO output is normally in

high-impedance state and it is active only during Write and

Read Cycles. A pull-up or pull-down resistor may be needed

in DO line if a floating logic signal can cause unintended

current consumption in other circuits where DO is con-

nected.

The Address and Data are transmitted MSB first. The Chip

Select signal CS must be low during the Cycle transmission.

CS resets the interface when high and it has to be taken high

between successive Cycles. Data is clocked in on the rising

edge of the SCL clock signal, while data is clocked out on the

falling edge of SCL.

The MicroWire interface mode can also support SPI inter-

face. The difference with normal SPI interface is that in

LP3936 the Read operation from a new address needs two

read cycles. If repetitive reads are made from the same

address, a correct value is obtained on every read cycle.

MicroWire Write Cycle

20081407

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