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PC87382 Folha de dados(PDF) 17 Page - National Semiconductor (TI) |
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PC87382 Folha de dados(HTML) 17 Page - National Semiconductor (TI) |
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17 / 72 page ![]() 2.0 Power, Reset and Clocks (Continued) Revision 1.2 17 www.national.com Figure 2. XOR Tree (Simplified Diagram) The maximum propagation delay through the XOR tree, from the first pin in the chain to XOR_OUT is 200 ns. 2.4.3 Test Mode Entry Sequence Table 5 shows the decoding values required to enter each test mode. The test modes are decoded from the TEST and TRIS strap pins and are latched into PC87382 on power up. Table 5. Test Mode Selection Test Mode TEST TRIS No Test Mode Selected 1 1 ICT 1 0 XOR Tree 0 1 Reserved exclusively for NSC use 0 0 VDD XOR_OUT Pin 17 Pin 18 Pin 48 Pin 1 Pin 15 Pin 16 |
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