AP0101CS datasheet(32/42 Pages) ONSEMI

32 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

Protocol

Single Write to Random Location

Figure 20 shows the typical WRITE cycle from the host to the AP0101CS.The first 2 bytes

indicate a 16-bit address of the internal registers with most-significant byte first. The

following 2 bytes indicate the 16-bit data.

Figure 20:

Single WRITE to Random Location

Sequential WRITE, Start at Random Location

This sequence (Figure 21) starts in the same way as the single WRITE to random location

(Figure 20). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte writes until “L” bytes have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 21:

Sequential WRITE, Start at Random Location

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Previous Reg Address, N

Reg Address, M

M+1

Write Data

Slave Address

A Reg Address[15:8]

Write Data

Reg Address[7:0]

Write Data

Previous Reg Address, N

Reg Address, M

M+1

M+2

M+1

M+3

Write Data

M+L-2

M+L-1

M+L

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

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