UCD3138RHAT datasheet(21/89 Pages) TI1

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UCD3138

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SLUSAP2G – MARCH 2012 – REVISED SEPTEMBER 2016

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Specifications

•

Phase control relative to other DPWM modules

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Sample trigger placement for output voltage sensing at any point during the DPWM cycle.

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Support for two independent edge placement DPWM outputs (same frequency or period setting)

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Dead-time between DPWM A and B outputs

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High Resolution capabilities – 250 ps

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Pulse cycle adjustment of up to ±8.192 µs (32768 × 250 ps)

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Active high/ active low output polarity selection

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Provides events to trigger both CPU interrupts and start of ADC12 conversions.

5.8.1.3

DPWM Events

Each DPWM can control the following timing events:

1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in

relationship to the DPWM period. The programmed value set in the register should be one fourth of the

value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the

circuitry runs at one fourth of the DPWM clock (PCLK = 250 MHz max). When this sample trigger

count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC,

resulting in a CLA calculation, and a DPWM update. Oversampling can be set for 2, 4, or 8 times the

sampling rate.

2. Phase Trigger Count – count offset for slaving another DPWM (Multi-Phase/Interleaved operation).

3. Period – low resolution switching period count. (count of PCLK cycles)

4. Event 1 – count offset for rising DPWM A event. (PCLK cycles)

5. Event 2 – DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are

for high resolution control. Upper 14 bits are the number of PCLK cycle counts.

6. Event 3 – DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution

control. Upper 14 bits are the number of PCLK cycle counts.

7. Event 4 – DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution

control. Upper 14 bits are the number of PCLK cycle counts.

8. Cycle Adjust – Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the DPWM counter can create the desired

edge placements in the DPWM. High resolution edge capability is available on Events 2, 3, and 4.

Figure 5-6 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own

registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals

are used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional

DPWM modes are described below.

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