STV6889 datasheet(18/56 Pages) STMICROELECTRONICS

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STV6889

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6.8 DC/DC controller section

Note 46: A current sink is provided by the BComp output while BOut is disabled.

Note 47: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is

stabilized.

Note 48: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On”

edge with horizontal fly-back signal. Refer to chapter "DC/DC controller" for more details.

Table 5. DC/DC controller section

(VCC = 12V, Tamb = 25°C)

Symbol

Parameter

Test Conditions

Value

Units

Min.

Typ.

Max.

RB+FB

Ext. resistance applied between

BComp output and BRegIn input

AOLG

Open loop gain of error amplifier on

BRegIn input

Low frequency(19)

100

fUGBW

Unity gain bandwidth of error amplifier

on BRegIn input

(19)

6MHz

IRI

Bias current delivered by BRegIn

-0.2

IBComp

Output current capability of BComp out-

put.

BOut enabled

BOut disabled(46)

-0.5

0.5

2.0

ABISense

Voltage gain on BISense input

VThrBIsCurr

Threshold voltage on BISense input

corresponding to current limitation

ThrBlsense = 0

ThrBlsense = 1

TBD

2.1

1.2

IBISense

Bias current delivered by BISense

-1

tBOn

Conduction time of the power transistor

TH - 300ns

IBOut

Output current capability of BOut output

VBOSat

Saturation voltage of the internal output

transistor on BOut

IBOut=10mA

0.25

VBReg

Regulation reference for BRegIn volt-

age(47)

VRefO=8V

BREF (Sad03h):

x0000000b

x1000000b

x1111111b

3.8

4.9

6.0

tBTrigDel

Delay of BOut “Off-to-On” edge after

middle of flyback pulse (48)

BOutPh = 0 and BO-

HEdge = 0

/TH

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