CY23S08SC-2HT datasheet(2/8 Pages) CYPRESS

2 / 8 page

PRELIMINARY

CY23S08

Document #: 38-07265 Rev. *D

Page 2 of 8

Spread Aware™

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we

designed this product so as not to filter off the Spread

Spectrum feature of the Reference input, assuming it exists.

When a zero delay buffer is not designed to pass the SS

feature through, the result is a significant amount of tracking

skew which may cause problems in systems requiring

synchronization.

For more details on Spread Spectrum timing technology,

please see Cypress’s application note EMI Suppression

Techniques with Spread Spectrum Frequency Timing

Generator (SSFTG) ICs.

Notes:

1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.

2. Weak pull-down.

3. Weak pull-down on all outputs.

4. Weak pull-ups on these inputs.

Table 1. Select Input Decoding

CLOCK A1–A4

CLOCK B1–B4

Output Source

PLL Shutdown

Three-State

PLL

Driven

Three-State

PLL

Driven

Reference

Driven

PLL

Table 2. Available CY23S08 Configurations

Device

Feedback From

Bank A Frequency

Bank B Frequency

CY23S08–1

Bank A or Bank B

Reference

CY23S08–1H

Bank A or Bank B

Reference

CY23S08–2

Bank A

Reference

Reference/2

CY23S08–2H

Bank A

Reference

Reference/2

CY23S08–2

Bank B

2 X Reference

Reference

CY23S08–2H

Bank B

2 X Reference

Reference

CY23S08–3

Bank A

2 X Reference

Reference or Reference[1]

CY23S08–3

Bank B

4 X Reference

2 X Reference

CY23S08–4

Bank A or Bank B

2 X Reference

Pin Description

Signal

Description

1REF[2]

Input reference frequency, 5V tolerant input

CLKA1[3]

Clock output, Bank A

CLKA2[3]

Clock output, Bank A

4VDD

3.3V supply

GND

Ground

CLKB1[3]

Clock output, Bank B

CLKB2[3]

Clock output, Bank B

8S2[4]

Select input, bit 2

9S1[4]

Select input, bit 1

CLKB3[3]

Clock output, Bank B

CLKB4[3]

Clock output, Bank B

GND

Ground

VDD

3.3V supply

CLKA3[3]

Clock output, Bank A

CLKA4[3]

Clock output, Bank A

FBK

PLL feedback input

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