P89C668HBA datasheet(19/54 Pages) PHILIPS

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Philips Semiconductors

Preliminary data

P89C668

80C51 8-bit Flash microcontroller family

64KB ISP Flash with 8KB RAM

2001 Jul 27

Interrupt Priority Structure

The P89C668 has an 8 source four-level interrupt structure (see

Table 8).

There are 4 SFRs associated with the four-level interrupt. They are

the IE, IEN1, IP, and IPH. (See Figures 10, 11, 12, and 13.) The IPH

(Interrupt Priority High) register makes the four-level interrupt

structure possible. The IPH is located at SFR address B7H. The

structure of the IPH register and a description of its bits is shown in

Figure 12.

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

INTERRUPT PRIORITY LEVEL

Level 0 (lowest priority)

Level 1

Level 2

Level 3 (highest priority)

The priority scheme for servicing the interrupts is the same as that

for the 80C51, except there are four interrupt levels rather than two

as on the 80C51. An interrupt will be serviced as long as an interrupt

of equal or higher priority is not already being serviced. If an

interrupt of equal or higher level priority is being serviced, the new

interrupt will wait until it is finished before being serviced. If a lower

priority level interrupt is being serviced, it will be stopped and the

new interrupt serviced. When the new interrupt is finished, the lower

priority level interrupt that was stopped will be completed.

Table 8.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

IE0

N (L)1

Y (T)2

03H

SI01 (I2C)

—

2BH

TP0

0BH

IE1

N (L)

Y (T)

13H

TF1

1BH

RI, TI

23H

TF2, EXF2

3BH

PCA

CF, CCFn

n = 0–4

33H

NOTES:

1. L = Level activated

2. T = Transition activated

EX0

IEN0 (0A8H)

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables it.

BIT

SYMBOL

FUNCTION

IEN0.7

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

enabled or disabled by setting or clearing its enable bit.

IEN0.6

PCA interrupt enable bit

IEN0.5

ES1

I2C interrupt enable bit.

IEN0.4

ES0

Serial Port interrupt enable bit.

IEN0.3

ET1

Timer 1 interrupt enable bit.

IEN0.2

EX1

External interrupt 1 enable bit.

IEN0.1

ET0

Timer 0 interrupt enable bit.

IEN0.0

EX0

External interrupt 0 enable bit.

SU01460

ET0

EX1

ET1

ES0

ES1

Figure 10. IE Registers

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