Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

RSRC

RxOUT Setup to RxCLK OUT (Figure 7)

f = 40 MHz

6.5

14.0

ns

f = 66 MHz

2.5

8.0

ns

RHRC

RxOUT Hold to RxCLK OUT (Figure 7)

f = 40 MHz

6.0

8.0

ns

f = 66 MHz

2.5

4.0

ns

RCCD

RxCLK IN to RxCLK OUT Delay (Figure 9)

f = 40 MHz

4.0

6.7

8.0

ns

f = 66 MHz

5.0

6.6

9.0

ns

RPLLS

Receiver Phase Lock Loop Set (Figure 11)10

ms

RPDD

Receiver Powerdown Delay (Figure 15)1

µs

Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both

dependent on type/length of cable), and clock jitter less than 250 ps.

Note 6: The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.

Note 7: The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.

AC Timing Diagrams

01290902

FIGURE 1. “Worst Case” Test Pattern

01290903

01290904

FIGURE 2. DS90CR215 (Transmitter) LVDS Output Load and Transition Times

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