OPA698ID datasheet(21/32 Pages) TI1

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OPA698

SBOS258D

www.ti.com

OUTPUT LIMITERS

The output voltage is linearly dependent on the input(s) when

it is between the limiter voltages VH (pin 8) and VL (pin 5).

When the output tries to exceed VH or VL, the corresponding

limiter buffer takes control of the output voltage and holds it

at VH or VL. Because the limiters act on the output, their

accuracy does not change with gain. The transition from the

linear region of operation to output limiting is very sharp—the

desired output signal can safely come to within 30mV of VH

or VL with no onset of non-linearity. The limiter voltages

can be set to within 0.7V of the supplies (VL ≥ –VS + 0.7V,

VH ≤ +VS – 0.7V). They must also be at least 400mV apart

(VH – VL ≥ 0.4V). When pins 5 and 8 are left open, VH and

VL go to the default voltage limit; the minimum values are

given in the electrical specifications. Looking at Figure 20 for

the zero bias current case shows the expected range of

(VS – default limit voltages) = headroom.

voltages. The limiters’ DC accuracy depends on attention to

detail. The two dominant error sources can be improved as

follows:

• Power supplies, when used to drive resistive dividers that

set VH and VL, can contribute large errors (for example,

±5%). Using a more accurate source, and bypassing pins

5 and 8 with good capacitors, will improve limiter PSRR.

• The resistor tolerances in the resistive divider can also

dominate. Use 1% resistors.

Other error sources also contribute, but should have little

impact on the limiters’ DC accuracy:

• Reduce offsets caused by the Limiter Input Bias Currents.

Select the resistors in the resistive divider(s) as described

above.

• Consider the signal path DC errors as contributing to

uncertainty in the useable output swing.

• The limiter offset voltage only slightly degrades limiter

accuracy. Figure 21 shows how the limiters affect distor-

tion performance. Virtually no degradation in linearity is

observed for output voltage swinging right up to the limiter

voltages.

Limiter Headroom (V)

0.5

1.5

2.5

100

–25

–50

–75

–100

Maximum Over Temperature

Minimum

Over Temperature

Limiter Headroom = +V

S – VH

= V

L – (–VS)

Current = I

VH or –IVL

FIGURE 20. Limiter Bias Current vs Bias Voltage.

When the limiter voltages are more than 2.1V from the

supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use

simple resistor dividers to set VH and VL (see Figure 1). Make

sure to include the limiter input bias currents (Figure 8) in the

calculations (that is, IVL = –50µA out of pin 5, and IVH = +50µA

out of pin 8). For good limiter voltage accuracy, run at least

1mA quiescent bias current through these resistors. When

the limiter voltages need to be within 2.1V of the supplies (VL

≤ –V

S + 2.1V or VH ≥ +VS – 2.1V), consider using low

impedance buffers to set VH and VL to minimize errors due

to bias current uncertainty. This condition will typically be the

case for single-supply operation (VS = +5V). Figure 2 runs

2.5mA through the resistive divider that sets VH and VL. This

limits errors due to IVH and IVL < ±1% of the target limit

OUTPUT DRIVE

The OPA698 has been optimized to drive 500

Ω loads, such

as ADCs. It still performs very well driving 100

Ω loads; the

specifications are shown for the 500

Ω load. This makes the

OPA698 an ideal choice for a wide range of high-frequency

applications.

Many high-speed applications, such as driving ADCs, require

op amps with low output impedance. As shown in the typical

performance curve

Output Impedance vs Frequency, the

OPA698 maintains very low closed-loop output impedance

over frequency. Closed-loop output impedance increases

with frequency, since loop gain decreases with frequency.

± Limit Voltage (V)

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7 1.8

1.9

–40

–50

–60

–70

–80

–90

3rd-Harmonic

2nd-Harmonic

O = 0VDC ± 1VP

f = 5MHz

L = 500Ω

FIGURE 21. Harmonic Distortion Near Limit Voltages.

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