TNETX3150GGP datasheet(67/113 Pages) TI1

67 / 113 page

TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

port structures (continued)

QM for store-and-forward operation (see Figure 26)

Free Queue Register

Working Register

List of Empty External DRAM Buffers

Four-Entry,

Free-Buffer Stack

Channel 0

Channel 1

Channel 14

Channel 0

Channel 1

Channel 14

Length

Tail

Head

Tail

Length

Receive

Queue for

Channel 0

RX FIFO Buffers

1. RX FIFO buffer

receives frame data.

TX FIFO Buffers

6. Free buffer

returned to the

working buffer, first

entry in the stack, or

to the free queue if

stack is full.

2. Full FIFO buffer transferred to next free

DRAM buffer in stack or free queue.

3. Frame from receive queue 1

transferred by updating transmit

queue 14 pointers (in this case

four buffers are linked).

5. External buffer

moved from DRAM to

the TX FIFO and output

Head

Tail

Length

Tail

Head

Transmit Queue for

Other Channels

Transmit queue

for channel 14

4. Maximum transmit queue length

determined by register settings.

Receive Queue for

Other Channels

Figure 26. Queue Management for Store and Forward

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