UCD3138064ARGCT datasheet(24/83 Pages) TI1

24 / 83 page

IOFFSET

REA

EAP

EAN

AGND

IOFFSET

REA

Front End Differential

Amplifier

UCD3138064A

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

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Detailed Description

6.4.2.1.1 Front End

Figure 6-2 shows the block diagram of the front end module. It consists of a differential amplifier, an

adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging

filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert

with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range

with 6 bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended

result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output

could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE

value such that the minimum resolution is maintained that still allows the voltage to fit within the range of

the measurement. The EADC control logic receives the sample request from the DPWM module for

initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the filter

for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of

dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to

facilitate things like soft start, nested loops, etc. Some additional features include the ability to change the

polarity of the error measurement and an absolute value mode which automatically adds the DAC value to

the error.

It is possible to operate the controller in a peak current mode control configuration. In this mode topologies

like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The

internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope

compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward

performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this

buffer is specified in the Electrical Characteristics table.

Figure 6-2. Input Stage Of EADC Module

UCD3138064ARGCT Folha de dados(PDF) 24 Page - Texas Instruments