TLC532AI, TLC532AM, TLC533AI, TLC533AM

LinCMOS

™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS

WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS

SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986

POST OFFICE BOX 655303

5

PARAMETER MEASUREMENT INFORMATION

28

CLOCK #10

CLOCK #1

123

MS

Byte

MS

Byte

tacq

th(bus)

th(bus)

HI-Z

HI-Z

HI-Z

HI-Z

HI-Z

HI-Z

LS

Byte

LS

Byte

tsu(bus)

tsu(bus)

tdis

tdis

ten

ten

tsu(CS)

th(C)

tsu(A)

tr(CLK)

tf(CLK)

Start

Conversion

End

Conversion

CLK

R

(see Note A)

Control

Inputs

R/W

RS

CS

Data Bus,

Data Out

(READ)

Data Bus,

Data In

(WRITE)

(see Note B)

NOTES: A. The reset pulse (R low) is required only during powerup.

B. The most significant byte output of Data Out occurs when CLK is high. When CLK is low, Data Out is in the high-impedance (off) state.

When CLK goes high again, the least significant byte is placed on the data bus. At this point, the least significant byte remains on the

bus for as long as CLK is kept high.

Figure 1. Read or Write Cycle Voltage Waveforms