LP3913 datasheet(32/70 Pages) TI1

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ONSTAT

NRST

ONOFF

3 ms

POWERACK

VREFH

64 ms

5 ms

38 ms

43 ms

48 ms

58 ms

t2 t3

32 ms

deglitch

(Bit D4 in PON register and

POWERBACK pin)

VBUCK3

VBUCK2

VBUCK1

VLDO1, VLDO2

(To Microprocessor)

(From Microprocessor)

LP3913

SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

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Figure 57. Power Down Caused by External Event

Transition from Active to Standby Mode Due to Expiring POWERACK Deadline

With no external charger present when the system processor fails to acknowledge the power-on in time by

setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128 ms deadline following

the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources

will be disabled before transitioning to Standby Mode. This 2 ms delay allows the microprocessor to receive a

clean reset before the power is de-asserted. A new power-on event is then required to transition back to Active

mode.

With either external charger present when the system processor fails to acknowledge the power-on in time by

setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128 ms deadline following

the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources

will be disabled before transitioning to Charger Standby Mode.

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