SN65DP149 datasheet(13/54 Pages) TI1

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SN65DP149, SN75DP149

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SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016

Product Folder Links: SN65DP149 SN75DP149

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(1)

Cb = total capacitance of one bus line in pF.

7.12 DDC and I

2C Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rise time of both SDA and SCL signals

Vcc = 3.3-V

300

Fall time of both SDA and SCL signals

300

tHIGH

Pulse duration, SCL high

0.6

μs

tLOW

Pulse duration, SCL low

1.3

μs

tSU1

Setup time, SDA to SCL

100

tST, STA

Setup time, SCL to start condition

0.6

μs

tHD,STA

Hold time, start condition to SCL

0.6

μs

tST,STO

Setup time, SCL to stop condition

0.6

μs

t(BUF)

Bus free time between stop and start condition.

1.3

μs

tPLH1

Propagation delay time, low-to-high-level output

Source-to-sink: 100-kbps pattern;

Cb(Sink) = 400-pF(1);

See Figure 14

360

tPHL1

Propagation delay time, high-to-low-level output

230

tPLH2

Propagation delay time, low-to-high-level output

Sink to Source: 100-kbps pattern;

Cb(Source) = 100-pF(1);

See Figure 15

250

tPHL2

Propagation delay time, high-to-low-level output

200

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