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STA310 Folha de dados(PDF) 11 Page - STMicroelectronics |
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STA310 Folha de dados(HTML) 11 Page - STMicroelectronics |
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11 / 90 page ![]() 11/90 STA310 4.2 Clocks There are two embedded PLLs in the STA310: the system PLL and the PCM PLL. The following is the block diagram of the system and audio clocks used in the STA310 Figure 3. PLL Block Diagram Figure 4. Block Diagram of Functional PLL SPDIF PLL Audio PLL Sys plls_config 78 RXN RXP Periph 2 Periph 3 / N CLK CLKOUT Periph 1 W R I SCLOCK LRCLK PCMOUT0,1,2,3 PCMCLK pcm_clk sys_clk DSP Core PCM_OUT sys_clockout VCO Charge Pump DIV M+1 Switching Circuit DIV (X+1) PFD R C C3 Ip Uvco Frac dN Oclk analog part Filter (external) DIV N+1 ClkIn (27MHz) pll_disable update_frac |
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