DP8422V datasheet(39/60 Pages) NSC

Nome de Peças	DP8422V

Descrição Electrónicos	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

PDF	60 Pages

Scroll/Zoom	100%

Fabricante Electrônico	NSC [National Semiconductor (TI)]

Página de início	http://www.national.com

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39 / 60 page

100 Dual Accessing (DP8422V DP84T22) (Continued)

Since the DP8422V DP84T22 has only one set of address

inputs the signal is used with the addition of buffers to

allow the currently granted port’s addresses to reach the

DP8422V DP84T22 The signals which need to be buf-

ferred are R0 – 10

C0 – 10

B0 – 1

ECAS0–3

and

LOCK All other inputs are not common and do not have to

be buffered as shown in

Figure 34a If a Port which is not

currently granted tries to access the DRAM array the

GRANTB output will transition from a rising clock edge from

AREQ or AREQB negating and will precede the RAS for the

access by one or two clock periods GRANTB will then stay

in this state until the other port requests an access and the

currently granted port is not accessing the DRAM as shown

Figure 34b

TLF11109 – 59

If Port B is synchronous the Request Synchronizing logic will not be required

FIGURE 34a Dual Accessing with the DP8422V DP84T22 (System Block Diagram)

DP8422V Folha de dados(PDF) 39 Page - National Semiconductor (TI)