PCM1770

PCM1771

SLES011C – SEPTEMBER 2001 – REVISED MAY 2004

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21

MC

MS

MD

16-Bits

(1) Single Write Operation

MSB

LSB

MSB

(2) Continuous Write Operation

MSB

LSB

MSB

LSB

MSB

LSB

16-Bits x N Frames

MC

MS

MD

N Frames

Figure 26. Register Write Operation

CONTROL INTERFACE TIMING REQUIREMENTS (PCM1770)

Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper

control port operation.

t(MCH)

50% of VCC

MS

t(MLS)

LSB

50% of VCC

50% of VCC

t(MCL)

t(MHH)

t(MLH)

t(MCY)

t(MDH)

t(MDS)

MC

MD

PARAMETERS

SYMBOL

MIN

TYP

MAX

UNITS

MC pulse cycle time

t(MCY)

100(1)

ns

MC low-level time

t(MCL)

50

ns

MC high-level time

t(MCH)

50

ns

MS high-level time

t(MHH)

(2)

ns

MS falling edge to MC rising edge

t(MLS)

20

ns

MS hold time

t(MLH)

20

ns

MD hold time

t(MDH)

15

ns

MD set-up time

t(MDS)

20

ns

(1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128fS), where fS is sampling rate.

(2) 3/(128fS) s (min), where fS is sampling rate.

Figure 27. Control Interface Timing