CS4244 datasheet(28/63 Pages) CIRRUS

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DS900F2

CS4244

4.5

Serial Port Interface

The serial port interface format is selected by the Serial Port Format register bits. The TDM format is avail-

able in Slave Mode only.

4.5.1

TDM Mode

The serial port of the CS4244 supports the TDM interface format with varying bit depths from 16 to 24 as

shown in Figure 15. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC

on the rising edge.

As indicated in Figure 15, TDM data is received most significant bit (MSB) first, on the second rising edge

of the SCLK occurring after a FS/LRCK rising edge. All data is valid on the rising edge of SCLK. All bits

are transmitted on the falling edge of SCLK. Each slot is 32 bits wide, with the valid data sample left jus-

tified within the slot. Valid data lengths are 16, 18, 20, or 24 bits.

FS/LRCK identifies the start of a new frame and is equal to the sample rate, FS. As shown in Figure 14,

FS/LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data

sample and must be held valid for at least 1 SCLK period.

The structure in which the serial data is coded into the TDM slots is shown in Figure 16. SDOUT2 is un-

used in TDM mode and is placed in a high-impedance state. When using a 48 kHz sample rate with a

24.576 MHz MCLK and SCLK, a 16 slot TDM structure can be realized. When using a 48 kHz sample rate

with 12.288 MHz SCLK and 24.576 MHz MCLK, or a 96 kHz sample rate with a 24.576 MHz MCLK and

SCLK, an 8 slot TDM structure can be realized. The data that is coded into the TDM slots is extracted into

the appropriate signal path via the settings in the Control port. Please refer to Section 4.6.1 Routing the

Serial Data within the Signal Paths for more details.

SCLK

SDINx & SDOUT1

Channel 1

Channel 2

Channel N-1

Channel N

FS/LRCK

Frame

(N ≤ 16)

Figure 14. TDM System Clock Format

MSB

32-Bit Channel Block

LSB

24-Bit Audio Word

8-Bit Zero Pad

-1

-2

-3

-4

-5

-6

-7

Figure 15. 32-bit Receiver Channel Block

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