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AT89C5132-ROTIL Folha de dados(PDF) 3 Page - ATMEL Corporation

Nome de Peças AT89C5132-ROTIL
Descrição Electrónicos  USB Microcontroller with 64K Bytes Flash Memory
PDF  33 Pages
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Fabricante Electrônico  ATMEL [ATMEL Corporation]
Página de início  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT89C5132-ROTIL Folha de dados(HTML) 3 Page - ATMEL Corporation

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4256B–USB–03/06
AT89C5132
ISP Communication
Management
The purpose of this process is to manage the communication and its protocol between the on-
chip bootloader and an external device (host). The on-chip bootloader implements a USB proto-
col (see Section “Protocol”, page 12). This process translates serial communication frames
(USB) into Flash memory accesses (read, write, erase...).
User Call Management
Several Application Program Interface (API) calls are available to the application program to
selectively erase and program Flash pages. All calls are made through a common interface (API
calls) included in the bootloader. The purpose of this process is to translate the application
request into internal Flash memory operations.
Flash Memory
Management
This process manages low level accesses to the Flash memory (performs read and write
accesses).
Bootloader Configuration
Configuration and
Manufacturer
Information
The following table lists Configuration and Manufacturer byte information used by the boot-
loader. This information can be accessed through a set of API or ISP commands.
Mapping and Default
Value of Hardware
Security Byte
The 4 MSB of the Hardware Byte can be read/written by software (this area is called Fuse bits).
The 4 LSB can only be read by software and written by hardware using parallel programmer
devices, this area is called Lock bits.
Note:
U: Unprogrammed = 1
P: Programmed = 0
Table 1. Configuration and Manufacturer Information
Mnemonic
Description
Default Value
BSB
Boot Status Byte
FFh
SBV
Software Boot Vector
FOh
SSB
Software Security Byte
FFh
EB
Extra Byte
FFh
Manufacturer
58h
Id1: Family Code
D7h
Id2: Product Name
F7h
Id3: Product Revision
DFh
Table 2. Hardware Byte Information
Bit Position
Mnemonic
Default Value
Description
7
X2B
U
To start in x1 mode
6
BLJB
P
To map the boot area in code area between F000h-FFFFh
5
U
4
U
3
reserved
U
2
LB2
P
To lock the chip (see datasheet)
1
LB1
U
0
LB0
U



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