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DS90UR910-Q1 Folha de dados(PDF) 3 Page - Texas Instruments

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Nome de Peças DS90UR910-Q1
Descrição Electrónicos  10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter
PDF  34 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
Logo TI1 - Texas Instruments

DS90UR910-Q1 Folha de dados(HTML) 3 Page - Texas Instruments

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DS90UR910-Q1
40-Pin WQFN
(Top View)
VDDA
RIN-
GND
CMF
GND
CMLOUT-
RIN+
CMLOUT+
VDDA
VDDP
VDDCSI
DATA1+
DATA1-
GND
DATA0+
DATA0-
GND
CLK+
CLK-
CONFIG[0]
DAP = GND
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DS90UR910-Q1
www.ti.com
SNLS414D – JUNE 2012 – REVISED JULY 2015
Product Folder Links: DS90UR910-Q1
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
(1)
1 = HIGH, 0 = LOW
4 Pin Configuration and Functions
40-Pin WQFN
Top View
Pin Descriptions (1)
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Serial Interface
RIN+
RIN-
33
34
I, CML
Inverting and non-inverting differential inputs. The inputs must be AC Coupled with a 100 nF
capacitor.
CMF
35
I, Analog
Common mode filter pin for the differential inputs. CMP is the virtual ground of the differential
input stage. A bypass capacitor is connected from CMP to ground to increase the receiver’s
common mode noise immunity. A 4.7 µF ceramic capacitor is recommended.
CMLOUT+
CMLOUT-
37
38
O, CML
Inverting and non-inverting differential outputs. Single 100
Ω (1%) termination resistor must
be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer
and requires use of the Serial Control Bus to enable.
MIPI Interface
DATA1+
DATA1-
19
18
O, DPHY
O, DPHY
Inverting and non-inverting data output of DPHY Lane 1
DATA0+
DATA0-
16
15
O, DPHY
O, DPHY
Inverting and non-inverting data output of DPHY Lane 0
CLK+
CLK-
13
12
O, DPHY
O, DPHY
Inverting and non-inverting half-rate DPHY clock lane



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