ADS7828

11

SBAS181B

www.ti.com

READING DATA

Data can be read from the ADS7828 by read-addressing the

part (LSB of address byte set to 1) and receiving the

transmitted bytes. Converted data can only be read from the

ADS7828 once a conversion has been initiated as described

in the preceding section.

Each 12-bit data word is returned in two bytes, as shown

below, where D11 is the MSB of the data word, and D0 is the

LSB. Byte 0 is sent first, followed by Byte 1.

modes. It may be desirable to remain in HS mode after

reading a conversion; to do this, issue a repeated START

instead of a STOP at the end of the read sequence, since a

STOP causes the part to return to F/S mode.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS7828 circuitry. The basic SAR

architecture is sensitive to glitches or sudden changes on the

power supply, reference, ground connections, and digital

inputs that occur just prior to latching the output of the analog

comparator. Therefore, during any single conversion for an

“n-bit” SAR converter, there are n “windows” in which large

external transient voltages can easily affect the conversion

result. Such glitches might originate from switching power

supplies, nearby digital logic, and high-power devices.

With this in mind, power to the ADS7828 should be clean and

well-bypassed. A 0.1

µF ceramic bypass capacitor should be

placed as close to the device as possible. A 1

µF to 10µF

capacitor may also be needed if the impedance of the

The ADS7828 architecture offers no inherent rejection of

noise or voltage variation in regards to using an external

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital results.

While high-frequency noise can be filtered out, voltage varia-

tion due to line frequency (50Hz or 60Hz) can be difficult to

remove.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections that are too near the grounding point of a

microcontroller or digital signal processor. The ideal layout

will include an analog ground plane dedicated to the con-

verter and associated analog circuitry.

MSB

6

5

43

21

LSB

BYTE 0

0

0

0

0

D11

D10

D9

D8

BYTE 1

D7

D6

D5

D4

D3

D2

D1

D0

READING IN F/S MODE

Figure 3 describes the interaction between the master and

the slave ADS7828 in Fast or Standard (F/S) mode. At the

end of reading conversion data the ADS7828 can be issued

a repeated START condition by the master to secure bus

operation for subsequent conversions of the A/D converter.

This would be the most efficient way to perform continuous

conversions.

READING IN HS MODE

High Speed (HS) mode is fast enough that codes can be

read out one at a time. In HS mode, there is not enough time

for a single conversion to complete between the reception of

a repeated START condition and the read-addressing byte,

so the ADS7828 stretches the clock after the read-address-

ing byte has been fully received, holding it LOW until the

conversion is complete.

See Figure 4 for a typical read sequence for HS mode.

Included in the read sequence is the shift from F/S to HS

FIGURE 3. Typical Read Sequence in F/S Mode.

Sr

A1

100

1

0

A0

R

A

00

00

D11 D10 D9 D8

AD7 D6 . . .D1 D0

NP

SA1

10

010

A0

W

ASD

C2 C1 C0 PD1 PD0 XXA

ADC Power-Down Mode

ADC Sampling Mode

Write-Addressing Byte

Command Byte

See

Note A

Read-AddressingByte

2

×(8 bits + ack/not-ack)

From master to slave

From slave to master

ADC Power-Down Mode

(Depends on Power-Down Selection Bits)

W = 0 (WRITE)

R = 1 (READ)

ADC Converting Mode

A = acknowledge (SDA Low)

N = not-acknowledge (SDA High)

S = START Condition

P = STOP Condition

Sr = repeated START Condition

NOTE: (A) Use repeated START to secure bus operation and loop back to the stage of write-addressing for next conversion.