ACD2204 datasheet(8/20 Pages) ANADIGICS

8 / 20 page

PRELIMINARY DATA SHEET - Rev 1.0

04/2003

ACD2204

0000000

00000

0000000

0000

-------

------

1111111

111111

LOGIC PROGRAMMING

Notes:

Divide ratios less than 3 are prohibited.

LSB

MSB

Synthesizer Register Programming

The ACD2204 includes two PLL synthesizers. Each

synthesizer contains programmable Reference and

Main dividers, which allow a wide range of local

oscillator frequencies. The 22-bit registers that control

the dividers are programmed via a shared three-wire

bus, consisting of Data, Clock and Enable lines.

The data word for each register is entered serially

in order with the most significant bit (MSB) first and

the least significant bit (LSB) last. The rising edge

of the Clock pulse shifts each data value into the

of the data entry, then set high to latch the data into

the register. (See Figure 4.)

The two least significant bits of each register are

programmed during a particular data entry cycle.

Table 7 indicates the register select bit settings used

to program each of the available registers.

Table 7: Register Select Bits

Table 9: Reference Divider R Counter Bits

Table 8: Reference Divider Registers

Reference Divider Programming

The reference divider register for each synthesizer

consists of fifteen divider bits, five program mode

bits and the two register select bits, as shown in

Table 8. The fifteen divider bits allow a divide ratio

from 3 to 32767, inclusive, as shown in Table 9.

ACD2204 Folha de dados(PDF) 8 Page - ANADIGICS, Inc

ACD2204 Folha de dados(HTML) 8 Page - ANADIGICS, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Folha de dados Download

Ligação URL