ADC0851 datasheet(21/38 Pages) TI1

21 / 38 page

20 Memory Access Modes (Continued)

The address bits access specific memory locations as per

Table II(a) and (b) for the ADC0851 and ADC0858 respec-

tively The address data is clocked in with the MSB (bit A3)

first

The timing diagram in

Figure 5 shows that after CS goes

low the first four bits of the input word configure the device

to ‘‘read one limit’’ mode Next the address bits select the

desired memory location Third clock rising edge after the

address data’s LSB is loaded the limit data is output with

the LSB (bit L0) first

24 READ ALL LIMITS MODE

With a mode address of1111 the device is configured in

the ‘‘read all limits mode’’ When in this mode 8-bit limit

data from each memory location is serially transmitted out

The data format for the input word is as follows

Data Input (DI) WordADC0851 or ADC0858

TLH11021 – 36

Note that no memory address data is required The limit

data is sequentially transmitted out starting from the memo-

ry location for CH0 – Lower Limit and ending at CH1 – Upper

Limit for the ADC0851 (see Table II(a)) CH7 – Upper Limit

for the ADC0858 (see Table II(b))

The timing diagram of

Figure 6 shows that the input data is

loaded starting at the first rising edge of CLK after CS goes

low Third clock rising edge after the last bit of the input data

is loaded the limit data is serially transmitted out Four limit

words are transmitted for the ADC0851 sixteen for the

ADC0858 Each limit word is output with the LSB (bit L0)

first Taking CS high after the MSB of the last limit data is

transmitted completes the operation

TLH11021 – 38

FIGURE 5 Timing Diagram for Read One Limit ADC0851ADC0858

TLH11021 – 39

FIGURE 6 Timing Diagram for Read All Limits ADC0851ADC0858

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