TDA8029HLSLASHC2 datasheet(23/58 Pages) PHILIPS

23 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

Notes

1. Details on interaction with the UART behaviour in Power-down mode are described in Section 8.15.

2. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value

read from a reserved bit is indeterminate.

8.4.2

INTERRUPT PRIORITY (IP) REGISTER

Table 24 Interrupt priority register bits

Table 25 Description of register bits

Note

1. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value

read from a reserved bit is indeterminate.

8.4.3

INTERRUPT PRIORITY HIGH (IPH) REGISTER

Table 26 Interrupt priority high register bits

Table 27 Description of register bits

EX1

External interrupt 1 enable. EX1 = 1 enables the interrupt; EX1 = 0 disables the

interrupt.

ET0

Timer 0 interrupt enable. ET0 = 1 enables the interrupt; ET0 = 0 disables the interrupt.

EX0

External interrupt 0 enable. EX0 = 1 enables the interrupt; EX0 = 0 disables the

interrupt.

BIT

543210

Symbol

−−

PT2

PT1

PX1

PT0

PX0

BIT

SYMBOL

DESCRIPTION

7 and 6

−

Not implemented. Reserved for future use; note 1.

PT2

Timer 2 interrupt priority. See Table 20.

4PS

Serial port interrupt priority. See Table 20.

PT1

Timer 1 interrupt priority. See Table 20.

PX1

External interrupt 1 priority. See Table 20.

PT0

Timer 0 interrupt priority. See Table 20.

PX0

External interrupt 0 priority. See Table 20.

BIT

543210

Symbol

−−

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

BIT

SYMBOL

DESCRIPTION

7 and 6

−

Not implemented. Reserved for future use; note 1.

PT2H

Timer 2 interrupt priority. See Table 20.

PSH

Serial port interrupt priority. See Table 20.

PT1H

Timer 1 interrupt priority. See Table 20.

BIT

SYMBOL

DESCRIPTION(1)

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