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PCI9060ES Folha de dados(PDF) 43 Page - List of Unclassifed Manufacturers

Nome de Peças PCI9060ES
Descrição Electrónicos  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
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PCI9060ES Folha de dados(HTML) 43 Page - List of Unclassifed Manufacturers

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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
©PLX Technology, Inc., 1997
Page 34
Version 1.02
3.8 VENDOR AND DEVICE ID
REGISTERS
Three Vendor and Device ID registers are supported:
•
(LOC:00h), which contains the normal Device and
Vendor IDs. This register can be loaded from the
serial EEPROM or from local processors.
•
(LOC:2Ch), which contains the Subsystem and
Subvendor IDs. This register can be loaded from the
serial EEPROM or from local processors.
•
(LOC:F0h), which contains the hardcoded PLX
Vendor and Device IDs.
3.9 DOORBELL REGISTERS
There are two 32 bit doorbell interrupt/status registers in
the PCI 9080. One is assigned to the PCI bus interface
and the other is assigned to the local bus interface.
The local processor can generate a PCI bus interrupt by
writing any number other than all zeroes to the PCI to
Local Doorbell Register (refer to Table 4-56).
A PCI host can generate a local bus interrupt by writing
any number other than all zeroes to the Local to PCI
Doorbell Register (refer to Table 4-57).
3.10 MAILBOX REGISTERS
There are eight 32 bit mailbox registers in the PCI 9080
that can be written to and read from both buses. These
registers can be used to pass command and status
information directly between local and PCI bus devices.
A local interrupt can be generated, if enabled, when the
PCI host writes to one of the first four mailbox registers.
3.11 USER INPUT AND OUTPUT
PCI 9080 supports user input and output pins, USERI
(pin 31) and USERO (pin 27), respectively. User output
data can be logged by writing to bit 16 of (LOC:ECh).
User input data can be read from bit 17. (Refer to Table
4-59.)



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