TTP259-ASFN datasheet(19/81 Pages) TONTEK

19 / 81 page

Preliminary

TTP259

TonTouch

2015/05/25

Page 19 of 81

Ver: 1.1

The maximum period of WDT =(TB1OV cycle time) * 8

S-7: Low Voltage Reset (LVR)

The low voltage reset (LVR) forces the MCU in reset state during power

failure, especially as MCU working in AC power application, preventing from

abnormal state is the key issue. The LVR voltage can be select 2.2V, 3.0V by

mask option.

S-8: Reset

The chip has six kinds of reset sources: POR (power on reset), External

reset, Watch dog timer reset, LVR (low voltage reset), Burn out reset and

ROM fail reset. The reset feature can be divided into 2 kind groups that one

is system reset and the other is CPU reset. The system reset will initialize

the CPU and peripheral device with default state. The CPU reset only

initializes the CPU state and keeps the peripheral state no change.

.POR (power on reset)

The chip provides automatically reset function when the power is

turned on. The VDD should be below 0.5V and its rising slope (from

0.1VDD up to 0.9VDD) needs less than 10ms.

.External reset (RSTB)

This is one kind of system reset signal, but only forced externally.

When the chip acknowledged the low level from the pin RSTB exceed 1 us,

it will generate the reset procedure to reset CPU and all the peripheral back

to their initial state (default values).

WDT

Overflow

TFF

POR+RESET

SLEEP, STOP

INTF write $F first then

write CLRWDT after

DFF

TB1OV

Figure: Watch Dog Timer circuit

TTP259-ASFN Folha de dados(PDF) 19 Page - Tontek Design Technology