MB9DF565MLE datasheet(42/109 Pages) SPANSION

42 / 109 page

D at aS he e t

May 15, 2015, MB9D560_DS708-00001-3v0-E

CONFIDENTIAL

8. Handling Devices

For Latch-up Prevention

If a voltage higher than VCC5 or VCC12, or a voltage lower than VSS is applied to an I/O pin, or if a voltage

exceeding the ratings is applied between VCC5 to VSS and VCC12 to VSS pins, a latch-up may occur in

CMOS IC. If the latch-up occurs, the power supply current increases excessively and device elements may

be damaged by heat. Take care to prevent any voltage from exceeding the maximum ratings in device

application.

Also, the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1,

RVRH0, RVEH1) and analog input must not exceed the digital power supply (VCC5) when the power supply

to the analog system is turned on or off.

In the correct power-on sequence, turn on the digital power supply voltage (VCC5, VCC12) and analog

power supply voltages (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1, RVRH0,

RVRH1) simultaneously. Alternatively, turn on the digital power supply voltage (VCC5) first, and then turn on

the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1,

RVRH0, RVRH1).

Treatment of Unused Pins

If unused input pins are left open, they may cause a permanent damage to the device due to device

malfunction or latch-up. Connect a 2 kΩ or higher resistor to each of unused input pins for pull-up or

pull-down processing.

Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the

input state and treated in the same way as for the input pins.

MB9DF565MLE Folha de dados(PDF) 42 Page - SPANSION