PI6CFGL202BLIE datasheet(2/8 Pages) PERICOM

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03/03/15

PI6CFGL202B

Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs

Pin Description

Pin # Pin Name

Type

Description

Input

Select pin 0 (Internal pull-up resistor). See Table 1.

Input

Select pin 1 (Internal pull-up resistor). See Table 1.

SS0

Input

Spread Select pin 0 (Internal pull-up resistor). See Table 2.

XTAL_IN

Input

Crystal or clock input. Connect to a 25MHz crystal or single ended clock.

XTAL_OUT Output

Crystal connection. Leave unconnected for clock input.

Input

Output enable. Internal pull-up resistor.

GNDX

Power

Crystal ground pin.

SS1

Input

Spread Select pin 1 (Internal pull-up resistor). See Table 2.

VDDDIG3.3 Power

3.3V digital power.

CLK1#

Output

HCSL compliment clock output, LOW when output is disabled.

CLK1

Output

HCSL clock output, LOW when output is disabled.

VDDO

Power

Power supply, nominal 1.8V, range1.05V~3.3V.

GNDA

Power

Output and analog circuit ground.

CLK0#

Output

HCSL compliment clock output, LOW when output is disabled.

CLK0

Output

HCSL clock output, LOW when output is disabled.

VDDA3.3

Power

3.3V power supply for PLL core.

Table 1: Frequency Select Table

CLK(MHz)

100

125

200

Table 2: Spread Selection Table

SS1

SS0

Spread

No Spread

Down -0.5

Down -0.75

No Spread

15-0025

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