PI6C5916004 datasheet(7/12 Pages) PERICOM

7 / 12 page

PI6C5916004 Rev C

10/27/2014

PI6C5916004

6 GHz 1:4 LVPECL Fanout Buffer with Internal Termination

Application information

Suggest for Unused Inputs and Outputs

LVCMOS Input Control Pins

It is suggested to add pull-up=4.7k and pull-down=1k for LVC-

MOS pins even though they have internal pull-up/down but

with much higher value (>=50k) for higher design reliability.

REF_IN=/ REF_IN- Input Pins

They can be left floating if unused. For added reliability, connect

1kΩ to GND.

Outputs

All unused outputs are suggested to be left open and not con-

nected to any trace. This can lower the IC power supply power.

Power Decoupling & Routing

VDD Pin Decoupling

As general design rule, each VDD pin must have a 0.1uF decou-

pling capacitor. For better decoupling, 1uF can be used. Locat-

ing the decoupling capacitor on the component side has better

decoupling filter result as shown in Fig. 1.

Fig 1: Placement of Decoupling caps

Differential Clock Trace Routing

Always route differential signals symmetrically, make sure

there is enough keep-out space to the adjacent trace (>20mil.). In

156.25MHz XO drives IC example, it is better routing differen-

tial trace on component side as the following Fig. 2.

Clock timing is the most important component in PCB design, so

its trace routing must be planned and routed as a first priority in

manual routing. Some good practices are to use minimum vias (to-

tal trace vias count <4), use independent layers with good reference

plane and keep other signal traces away from clock traces (>20mil.)

etc.

Fig 2: IC routing for XO drive

Clock IC Device

VDD

0.1uF

GND

VDD

Decouple cap.

on comp. side

GND

Clock IC Device

REF_IN-

REF_IN+

VDD

GND

Keep out board vias

VDD

GND

150

156.25M XO

0.1uf

*100

*100 is optional if IC has

GND

14-0181

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